In integrated circuits that comprise output stages for driving discrete power devices or themselves integrated on the same chip containing the control circuitry, it is common to use a bootstrap capacitor to ensure correct powering of the driving stage. In these systems, it is essential that the bootstrap capacitor be charged in very short periods of time and this is usually attained using a diode emulator LDMOS transistor to rapidly charge the bootstrap capacitor.
In the case of a driving circuit for a so-called High Side Driver (HSD) of a half-bridge output stage, the LDMOS transistor should be capable of charging the bootstrap capacitance when the HSD is referred to low voltage (that is, when its output is low). The LDMOS transistor should emulate a high impedance when the HSD is referred to high voltage (that is, when its output is high). These functioning conditions must also be ensured during the HSD switching phase from high to low voltage or vice versa. This should be so despite possible current injections deriving from charging and discharging the capacitances associated with the LDMOS integrated structure that must sustain the high voltage supply of the power device.
The publication WO 94/27370 discloses a half-bridge circuit comprising a driving module of the lower device, and a floating driving module of the higher power device. The driving module of the high side transistor is realized in an isolated well region, and a properly controlled LDMOS transistor emulates a high voltage charging diode of a bootstrap capacitor.
In these cases it is necessary to control the effects of the parasitic bipolar junction transistors associated with an LDMOS integrated structure. The document EP-A-0743752, points out and describes certain conditions that originate problems related to the switch-on of parasitic transistors of the LDMOS integrated structure. The reference also describes different circuit layouts capable of averting current consumption caused by the switch-on of the parasitic transistors of the LDMOS integrated structure, and which avoid the occurrence of conditions that may cause the destruction of the integrated device itself.
The above cited European patent application EP-A-0743752, is herein incorporated by way of direct reference. FIG. 1 highlights the protecting circuit device described in the European patent application. According to the approach described in the European patent application, there exists a functioning phase of the integrated circuit, referred to as UVLO, when the voltage supply Vs is less than the minimum switch-on voltage of the entire integrated device including also the LDMOS transistor. During this time, with SW1 and SW2 both open, the potential of the body node VB of the LDMOS structure is kept at the circuit ground potential.
On the other hand, these so-called multipurpose integrated devices may be useful in many applications, during a UVLO phase, for charging the bootstrap capacitance (C). In this case, if the LDMOS body structure is connected to ground, its efficiency in charging the bootstrap capacitance is considerably diminished. In fact, in this case the gate-drain voltage (Vgd) must be many Volts to keep the LDMOS integrated transistor in a conducting state, and to account for the notable body effect that would increase its threshold voltage (Vth).
In addition, by keeping the body of the LDMOS structure at ground during this function phase, when the threshold voltage of the UVLO control signal has a particularly high value (often greater than 10V in the case of fabrication processes referred to as BCD off-line) there exists the risk of a breakdown of the base-emitter junction of the parasitic bipolar transistor (P2 in the scheme of FIG. 2).